Data centers
Hyperscale and colocation facilities running high-density AI racks.
Hayagreeva HEx
Direct-to-chip liquid cooling cold plate
Engineered for next-generation AI accelerators — continuous heat removal at the semiconductor package, with a copper-matrix path from die to facility rejection.
Product overview
HEx is the Hayagreeva Exchange — a direct-to-chip cold plate that mounts on the accelerator package. Fluid removes waste heat at the die and transfers it through the rack manifold and CDU to the facility heat-rejection system.
Package-specific fitting, mounting, connectors, and fluid are required for NVIDIA, AMD, and Intel accelerator architectures.
5,000+ W
Continuous heat removal
0.005
°C/W rated thermal resistance
4,000+
m²/m³ wetted surface area
May '26
Product launch
Why Hayagreeva HEx
Rated at the die
Continuous heat removal above 5,000 W at 0.005 °C/W — capacity stated at the package, not averaged across the rack.
Copper matrix
Wetted surface density above 4,000 m²/m³ expands the heat-transfer interface at the chip boundary.
Facility-ready path
Chip → HEx → CDU → rejection. One path moves heat off the package and out of the building.
Performance
Rated thermal capacity and resistance are stated at the semiconductor package under defined test conditions. System-level performance depends on coolant properties, flow rate, inlet temperature, pressure drop, and package geometry.
5,000+ W
Continuous heat removal (rated at package)
0.005 °C/W
Rated thermal resistance
~25 °C
Implied ΔT at rated conditions
4,000+
m²/m³ wetted surface area
Technical specifications
| Thermal capacity | More than 5,000 W continuous heat removal (rated at package) |
|---|---|
| Thermal resistance | 0.005 °C/W rated |
| Architecture | Copper matrix with 4,000+ m²/m³ wetted surface area |
| Compatibility | NVIDIA, AMD, and Intel accelerator architectures |
| Intellectual property | 14 patent filings supporting the thermal design |
| Launch | May 28, 2026 |
Exact results depend on coolant, flow rate, inlet temperature, and package geometry.
Validation & testing
Validated under stated conditions
Thermal performance is validated against stated test conditions. Rated metrics are separated from design targets. Contact engineering for NDA test documentation.
| Test methodology | Package-level thermal testing with documented coolant, flow, and inlet conditions |
|---|---|
| Claims policy | No unsupported superlatives; patent filings referenced as filings unless granted |
Applications
OEM platforms
Server and accelerator platforms requiring package-specific thermal integration.
System integrators
Custom HPC and sovereign AI programs with facility-level cooling constraints.
HPC & AI
Sustained accelerator performance without thermal throttling under load.
Request a pilot evaluation
Open for qualified data-center operators, server OEMs, and integration partners.
Contact engineering